Method for reading out or in a status from or to a ferroelectrical transistor of a memory cell and memory matrix

ABSTRACT

The state is read out from the ferroelectric transistor or stored in the ferroelectric transistor. During the read-out or storage of the state, at least one further ferroelectric transistor in the memory matrix is driven in such a way that it is operated in its depletion region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method for reading out and storing the statefrom or in a ferroelectric transistor of a memory cell and to a memorymatrix.

2. Description of the Related Prior Art

Such a method and such a memory matrix are disclosed in T. Nakamura etal. A Single-Transistor Ferroelectric Memory Cell, IEEE InternationalSolid-State Circuits Conference, ISSCC95, Session 4, TechnologyDirections: Displays, Photonics and Ferroelectric Memories, pp. 68-69,1995.

The memory matrix disclosed in T. Nakamura et al. A Single-TransistorFerroelectric Memory Cell, IEEE International Solid-State CircuitsConference, ISSCC95, Session 4, Technology Directions: Displays,Photonics and Ferroelectric Memories, pp. 68-69, 1995 is a matrix havinga multiplicity of memory cells each having a ferroelectric transistorwhich are connected to one another in a form of a square matrix.Furthermore, the memory matrix has a read-out/storage control device,which can be used to store a state of a ferroelectric transistor of amemory cell in the memory matrix or can be used to read out the presentstate of the corresponding ferroelectric transistor of the memory cell.

In accordance with the procedure described in T. Nakamura et al. ASingle-Transistor Ferroelectric Memory Cell, IEEE InternationalSolid-State Circuits Conference, ISSCC95, Session 4, TechnologyDirections: Displays, Photonics and Ferroelectric Memories, pp. 68-69,1995, if a state in a ferroelectric transistor of a memory cell of thememory matrix is stored, erased or read, a correspondingread-out/storage voltage is applied to the corresponding word lines andbit lines. The application of the required read-out/storage voltage alsoinfluences further ferroelectric transistors which lie adjacent in thememory matrix and are connected to the ferroelectric transistor whosestate is intended to be stored or read out. In this way, it can happenthat, as a result of the read-out or storage of a state of oneferroelectric transistor of the memory matrix, a state of a furtherferroelectric transistor of the memory matrix is altered erroneously,that is to say unintentionally.

As is described in T. Nakamura et al. A Single-Transistor FerroelectricMemory Cell, IEEE International Solid-State Circuits Conference,ISSCC95, Session 4, Technology Directions: Displays, Photonics andFerroelectric Memories, pp. 68-69, 1995, a read-out/storage voltage ofV_(pp)/V_(rr) is present at the ferroelectric transistor from or inwhich a state is intended to be read out or stored. In this case, aninterference voltage of approximately ±V_(pp)/2 or ±V_(pp)/3 is presentat the adjacent further ferroelectric transistors connected to the saidferroelectric transistor, and the state of the corresponding furtherferroelectric transistor can be erroneously altered by the saidinterference voltage.

This problem area will be explained below with reference to FIG. 2.

FIG. 2 illustrates a diagram 200 with a profile of the ferroelectricpolarization 201 in the gate of a ferroelectric transistor as a functionof an applied gate voltage V_(GS) 202. In the diagram 200 the gatevoltage 202 is specified in volts ([V]) and the ferroelectricpolarization 201 is specified in coulomb/m² ([C/m²]).

The profile of the ferroelectric polarization 201 as a function of thegate voltage V_(GS) 202 is described by a hysteresis loop 203. As can begathered from FIG. 2, a customary ferroelectric transistor has twostable polarization states, a first stable polarization state 204 and asecond stable polarization state 205. As a result of a change in theapplied gate voltage V_(GS), in particular as a result of anabove-described “interference voltage” of V_(pp)/2 or V_(pp)/3, thestate of the ferroelectric transistor can undergo transition along thehysteresis loop 203 into electrically non-distinguishable polarizationstates, namely into a first non-distinguishable polarization state 206and into a second non-distinguishable polarization state 207.

Whereas it is possible in a simple manner to electrically distinguishthe first distinguishable polarization state 204 from the seconddistinguishable polarization state 205, whereby two different states canbe realized and identified by the ferroelectric transistor within thememory matrix, such electrical distinguishability is not ensured in thecase of the non-distinguishable polarization states 206, 207.

Consequently, as a result of such an interference voltage, the statestored in adjacent further ferroelectric transistors in the memorymatrix can be altered or at least become undefined, in other words apolarization state is formed in the corresponding adjacent ferroelectrictransistor which cannot reliably be read out, that is to sayelectrically distinguished.

BRIEF SUMMARY OF THE INVENTION

A further ferroelectric transistor and a method for fabricating it aredescribed in U.S. Pat. No. 6,067,244 to Ma et al.

Jong-Son Lyu et al., Metal-Ferroelectric-Semiconductor Field-EffectTransistor (MFSFET) for Single Transistor Memory by Using Poly-SiSource/Drain and BaMgF₄ Dielectric, IEDM 1996, pp. 503-506, 1996describes a ferroelectric DRAM memory, each memory cell having aferroelectric field-effect transistor as its respective memory element.Furthermore, the ferroelectric DRAM memory contains a read and refreshcircuit coupled to the memory cells which serves for reading the datastored in the respective memory cells, by detecting the source/drainconductivity of the respective ferroelectric field-effect transistor,and for refreshing the data stored in the ferroelectric field-effecttransistors.

Consequently, the invention is based on the problem of reading out astate from a ferroelectric transistor or storing a state in aferroelectric transistor of a memory cell, which memory cell is arrangedin a memory matrix with a plurality of further memory cells with furtherferroelectric transistors, the intention being to avoid the situation inwhich the further ferroelectric transistors in further memory cells ofthe memory matrix are transferred into a non-distinguishablepolarization state as a result of the read-out or storage of aferroelectric transistor.

The problem is solved by means of the method for reading out or storinga state from or in a ferroelectric transistor of a memory cell and alsoby means of a memory matrix having the features in accordance with theindependent patent claims.

In a method for reading out or storing a state from or in aferroelectric transistor of a memory cell which is arranged in a memorymatrix with a plurality of further memory cells with furtherferroelectric transistors, the state is read out from the ferroelectrictransistor or stored in the ferroelectric transistor. At least onefurther ferroelectric transistor is driven during the read-out orstorage of the state in such a way that the further ferroelectrictransistor is operated in its depletion region.

A memory matrix has a plurality of memory cells connected to oneanother, at least some of the memory cells having at least oneferroelectric transistor. Furthermore, a readout/storage control deviceis provided in the memory matrix, which device controls a read-out orstorage of a state from or in a ferroelectric transistor of a memorycell of the memory matrix. The read-out/storage control device is set upin such a way that the state is read out from the ferroelectrictransistor or is stored in the ferroelectric transistor. Theread-out/storage control device is furthermore set up in such a way thatat least one further ferroelectric transistor in the memory matrix isdriven during the read-out or storage of the state in such a way thatthe further ferroelectric transistor is operated in its depletionregion.

The invention can clearly be seen in the fact that it has beenrecognized that, in order to programme a ferroelectric transistor in amemory cell, the said transistor must be brought into its inversionregion. However, an adjacent ferroelectric transistor of an adjacentmemory cell should not be programmed unintentionally, so that it shouldbe ensured that these are not brought into their respective inversionregion. This is ensured in that, according to the invention, at leastone further ferroelectric transistor in the memory matrix or all furtherferroelectric transistors in the memory matrix are operated in theirrespective depletion region during the read-out or storage of a statefrom or in the ferroelectric transistor.

Compared with the prior art, the invention makes it possible for thefirst time for the programming scheme of the ferroelectric transistorsin the memory matrix not to restrict the gate-bulk voltage (alsoreferred to as gate-substrate voltage below) of the furtherferroelectric transistors to V_(pp)/2 or V_(pp)/3, as is necessary inthe case of the programming scheme from T. Nakamura et al. ASingle-Transistor Ferroelectric Memory Cell, IEEE InternationalSolid-State Circuits Conference, ISSCC95, Session 4, TechnologyDirections: Displays, Photonics and Ferroelectric Memories, pp. 68-69,1995.

As a result, contrary to the procedure described in T. Nakamura et al. ASingle-Transistor Ferroelectric Memory Cell, IEEE InternationalSolid-State Circuits Conference, ISSCC95, Session 4, TechnologyDirections: Displays, Photonics and Ferroelectric Memories, pp. 68-69,1995, the bulk potential in the further ferroelectric transistors in thememory matrix can be kept constant.

Since, according to the invention, the entire bulk material does nothave to be subjected to charge reversal in this case, there is aconsiderable reduction both in the electric charge required forprogramming and in the time required for programming a ferroelectrictransistor in a memory matrix.

Thus, it has clearly been recognized according to the invention that thedisturb behaviour of a memory constructed from ferroelectric transistorsis crucially influenced by a suitable choice of the gate-source voltagewhich is applied to the further ferroelectric transistors, during theread-out or storage of a state from or in a ferroelectric transistor.

Preferred developments of the invention emerge from the dependentclaims.

The configurations described below relate both to the method and to theconfiguration of the read-out/storage control device, in which case, inaccordance with the corresponding development, the read-out/storagecontrol device is in each case set up in such a way that thecorresponding development is realized.

The corresponding configuration of the read-out/storage control devicecan be realized by means of a computer program which is provided in amemory of the read-out/storage control device and is executed by meansof a processor, in software or in hardware by means of an electronicspecial circuit.

In a preferred configuration of the invention, it is provided that thestate is read out from the ferroelectric transistor or stored in theferroelectric transistor by a read-out/storage voltage being applied tothe gate electrode of the ferroelectric transistor, for the purpose ofreading out or storing the state.

A plurality of transistors, in particular a plurality of ferroelectrictransistors, may be used in a memory cell of the memory matrix.

Even though a ferroelectric transistor which has been fabricated inaccordance with a specific method is used in the further exemplaryembodiment, an arbitrary further ferroelectric transistor cannonetheless be used in an alternative embodiment within the scope of theinvention.

Thus, in particular, it is possible to use different materials for thedielectric intermediate layer (in particular having a thickness ofbetween approximately 3 nm and 25 nm) of the ferroelectric transistor,which comprise, for example, cerium oxide CeO₂, hafnium oxide HfO₂,praseodymium oxide Pr₂O₃, zirconium oxide ZrO₂, titanium oxide TiO₂,tantalum oxide TaO₂ or dialuminium trioxide Al₂O₃.

By way of example, BMF (BaMgF₄), PZT ((PbZr)TiO₃) or SBT (SrBi₂Ta₂O₉)can be used as the ferroelectric layer. The ferroelectric layer has athickness of between approximately 30 nm and 300 nm.

Furthermore, the invention can also be used in the context of ap-channel ferroelectric transistor, even though the invention is clearlydescribed using an n-channel ferroelectric transistor in the furtherexemplary embodiment. In this case, it is necessary merely to reversethe polarity of the voltages that are to be correspondingly applied.

Moreover, it is possible to provide a plurality of electricalintermediate layers within a ferroelectric transistor which have one ormore of the materials described above.

Generally, an arbitrary insulator with the largest possible dielectricconstant and a high band gap can be used for the electrical intermediatelayer of the ferro electric transistor.

The ferroelectric layer can also be deposited directly on the substrateif the formation of disturbing intermediate layers can be avoided, forexample by epitaxial growth of the ferroelectric layer.

It should be noted in this connection that the invention is notrestricted to the structure of the ferro electric transistor describedin the exemplary embodiment, rather that, for example, the structure ofa ferro electric transistor which is described in T. Nakamura et al. ASingle-Transistor Ferroelectric Memory Cell, IEEE InternationalSolid-State Circuits Conference, ISSCC95, Session 4, TechnologyDirections: Displays, Photonics and Ferroelectric Memories, pp. 68-69,1995 or Jong-Son Lyu et al., Metal-Ferroelectric-SemiconductorField-Effect Transistor (MFSFET) for Single Transistor Memory by UsingPoly-Si Source/Drain and BaMgF₄ Dielectric, IEDM 1996, pp. 503-506, 1996can also readily be used within the scope of the invention.

The further ferroelectric transistor or a plurality of furtherferroelectric transistors in the memory matrix can be operated in theirdepletion regions during the read-out or storage of the state from theferroelectric transistor or in the ferroelectric transistor by thefurther ferroelectric transistors being driven in such a way that thegate-source voltages present at the further ferroelectric transistorsare less than the respective threshold voltage thereof.

This driving of the further ferroelectric transistor or transistors ispossible very simply and thus very cost-effectively without thepermanent properties of the ferroelectric transistors themselves havingto be altered.

Furthermore, the further ferroelectric transistor or transistors can beoperated in the respective depletion region by the further ferroelectrictransistor or transistors being driven in such a way that the followingholds true:V _(FB) −F(P _(FE))≦V _(GS) ≦V _(th) −F(P _(FE)),

-   -   where    -   V_(FB) designates the flat-band voltage of the further        ferroelectric transistor,    -   V_(GS) designates the gate-source voltage of the further        ferroelectric transistor,    -   V_(th) designates the threshold voltage of the further        ferroelectric transistor,    -   F(P_(FE)) designates a function of the ferroelectric        polarization P_(FE) of the further ferroelectric transistor.

In accordance with another development of the invention, the furtherferroelectric transistor or transistors is or are driven in such a waythat, in the respective further ferroelectric transistor, the appliedgate voltage is equal to the respectively applied source voltage and theapplied drain voltage.

This ensures that the gate-source voltage of the respective furtherferroelectric transistor is equal to the gate-drain voltage of thefurther ferroelectric transistor, namely has the value 0 volts, whichmeans that the gate-source voltage which is present at the respectivefurther ferroelectric transistor is always less than the thresholdvoltage thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

An exemplary embodiment of the invention is illustrated in the figuresand is explained in more detail below:

In the figures:

FIGS. 1 a to 1 d show a memory matrix having four memory cells eachhaving a ferroelectric transistor (FIG. 1 a), a voltage profile of anelectric voltage applied to the gate of a selected memory cell (FIG. 1b), a voltage profile of an electric voltage applied to the source of aselected memory cell (FIG. 1 c), and a diagram illustrating the profileof the polarization of the selected ferroelectric transistor as afunction of the gate-bulk voltage applied thereto;

FIG. 2 shows a diagram illustrating the profile of the ferroelectricpolarization in the gate of a customary ferroelectric transistor as afunction of the gate voltage present during the read-out or storage of astate from or in the ferroelectric transistor in accordance with theprior art;

FIG. 3 shows a sketch of a ferroelectric transistor in accordance withan exemplary embodiment of the invention;

FIG. 4 shows a flow diagram illustrating the individual steps forreading out or storing a state from or in a ferroelectric transistor inaccordance with an exemplary embodiment of the invention;

FIG. 5 shows a diagram illustrating the profile of the gate charge as afunction of the gate-bulk voltage present at a ferroelectric transistor;and

FIGS. 6 a to 6 c show a voltage profile of an electric voltage appliedto the gate of a further, non-selected memory cell (FIG. 6 a), a voltageprofile of an electric voltage applied to the source of the further,non-selected memory cell (FIG. 6 b), and a diagram illustrating theprofile of the polarization of the non-selected ferroelectric transistoras a function of the gate-bulk voltage applied thereto.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 a shows a memory matrix 100 having four memory cells 101, 102,103, 104.

Each memory cell 101, 102, 103, 104 has a ferroelectric transistor 105,106, 107, 108.

Furthermore, the memory matrix 100 has a first word line 109 and asecond word line 110.

Furthermore, the memory matrix 100 has a first bit line 111, a secondbit line 112, a third bit line 113 and a fourth bit line 114.

The gate 115 of the first ferroelectric transistor 105 and also the gate116 of the second ferroelectric transistor 106 are coupled to the firstword line 109.

The gate 117 of the third ferroelectric transistor 107 and the gate 118of the fourth ferroelectric transistor 108 are coupled to the secondword line 110.

The source 119 of the first ferroelectric transistor 105 and the source120 of the third ferroelectric transistor 107 are coupled to the firstbit line 111.

The drain 121 of the first ferroelectric transistor 105 and the drain122 of the third ferroelectric transistor 107 are connected to thesecond bit line 112.

The source 123 of the second ferroelectric transistor 106 and the source124 of the fourth ferroelectric transistor 108 are connected to thethird bit line 113.

The drain 125 of the second ferroelectric transistor 106 and the drain126 of the fourth ferroelectric transistor 108 are connected to thefourth bit line 114.

The word lines 109, 110 and also the bit lines 111, 112, 113, 114 areconnected to a read-out/storage control device 127.

Furthermore, the bulk terminals 128, 129 of the first ferroelectrictransistor 105 and of the second ferroelectric transistor 106 arecoupled to one another via a further electrical line 132.

Furthermore, the bulk terminals 130, 131 of the third ferroelectrictransistor 107 and of the fourth ferroelectric transistor 108 arecoupled to one another via a further electrical line 133.

The storage of a state of a ferroelectric transistor in the memorymatrix 100 and also the read-out of a state of a ferroelectrictransistor in the memory matrix 100 are controlled by theread-out/storage control device 127 by the application of differentvoltages to the corresponding word lines 109, 110 and/or to thecorresponding bit lines 111, 112, 113, 114, as is explained in moredetail below.

FIG. 3 shows a ferroelectric transistor 300, as is provided as the firstferroelectric transistor 105, as the second ferroelectric transistor106, as the third ferroelectric transistor 107 and as the fourthferroelectric transistor 108 in the memory matrix 100.

The ferroelectric transistor 300 has a p-doped substrate 301 made ofsilicon, and also a source region 302 and a drain region 303, adjoiningwhich two silicon oxide regions 304, 305 are arranged. These regions aredeposited by means of a customary CVD method. Afterwards, a dielectricintermediate layer 306 is deposited above the channel region 307 betweenthe source region 302 and the drain region 303 of the ferroelectrictransistor 300, made of silicon oxide. As an alternative, the dielectricintermediate layer 306 may also comprise a different dielectric, forexample Al₂O₃, CeO₂, ZrO₂, HfO₂, or Pr₂O₃, which is applied for examplewith the aid of a CVD method.

A ferroelectric layer 308 is then applied thereon for example with theaid of a CVD method, which layer may contain SBT (SrBi₂Ta₂O₉) or PZT((Pb,Zr)TiO₃).

The tempering of these two layers 306, 308 for setting the desired layerproperties can be effected in turn, that is to say after the depositionof each individual layer, but it can also be effected—if this isdesired—in one step after the deposition of both layers 306, 308.

The dielectric intermediate layer 306 and the ferroelectric layer 308are subsequently patterned by an etching process.

If a metallic gate electrode 309 is used, then it is produced by meansof a sputtering method and subsequently patterned by an etching process.

The metallic electrode can be used as a hard mask for the patterning ofthe layers situated underneath.

The implantation of the source region 302 and of the drain region 303can be effected in a self-aligned manner with respect to the gate stack.

The remaining process steps before and after the fabrication of theferroelectric gate stack can be effected analogously to standard CMOSmanufacturing methods.

Furthermore, the ferroelectric transistor 300 has contacts 310, 311,312, which are correspondingly conductively connected to the source 302,the drain 303 and the gate electrode 309.

Furthermore, the ferroelectric transistor 300 has a siliconplanarization layer 313.

The read-out and storage of a state in the first ferroelectrictransistor 105 is explained in more detail below with reference to FIG.4 and FIG. 1 b, FIG. 1 c and FIG. 1 d.

In a first step (step 401), in order to store a first state, a storagevoltage V_(pp), which is V_(pp)=5 V in accordance with the exemplaryembodiment, is applied to the first word line 109.

A gate-source voltage is applied across the gate of the respectivefurther ferroelectric transistors 106, 107, 108, as is explained in moredetail below.

To put it another way, this means that the gate voltage which isexplained in more detail below is applied to the non-selected secondword line 110 and a source voltage is applied to the non-selected thirdbit line 113 and a drain voltage which is explained in more detail belowis applied to the non-selected fourth bit line 114.

FIG. 1 b shows, in a first voltage diagram 140, a voltage profile 141 ofan electric voltage 142, applied to the first word line 109, as afunction of the time t 143 in seconds.

In particular, the first voltage diagram 140 illustrates a programmingregion 144, during which the first ferroelectric transistor 105 isprogrammed, that is to say is reprogrammed from an initial state “0” toa final state “1”, by the application of an electric voltage V_(pp)=5 V.

As is illustrated in the second voltage diagram 150 (cf. FIG. 1 c)associated with FIG. 1 b, during the programming of the firstferroelectric transistor 105, a voltage of 0 volts is applied to thefirst bit line 111 and to the second bit line 112, as can be gatheredfrom the voltage signal profile 151 of the second voltage diagram 150,in which the electric voltage 152 respectively present on the first bitline 111 and the second bit line 112 is illustrated as a function of thetime t 153 in seconds.

FIG. 1 d shows the polarization profile 163 of the selected firstferroelectric transistor 105 in a polarization diagram 160 illustratingthe polarization 161 in μC/cm² as a function of the gate-substratevoltage V_(GB) 162 in volts that is present.

FIG. 1 d shows that from the initial state “0” 164, by application ofthe electric voltage V_(pp)=5 V to the first word line 109, the firstferroelectric transistor 105 undergoes a transition to the final state“1” 165 along the hysteresis curve 166 in accordance with the profilesymbolized by arrows 167.

FIG. 1 d furthermore shows two plateau regions in the hysteresis loop166, a first plateau region 168 and a second plateau region 169, whichat least partly run essentially parallel to one another but aredisplaced relative to one another along the gate-substrate voltage 162and, furthermore, each have a different polarization, which is whatactually makes it possible to distinguish the two states 164, 165.

To put it another way, this means that the first ferroelectricfield-effect transistor 105 is programmed by the application of avoltage difference between the gate and the substrate terminal of thefirst ferroelectric transistor 105.

Given a suitable doping of the substrate and also a suitable gate oxidecapacitance of the first ferroelectric transistor 105, the gradient ofthe gate charge curve 501, as is illustrated by way of example in acharge diagram 500 in FIG. 5, is significantly larger in the inversionregion of the said transistor than in the depletion region of the saidtransistor.

FIG. 5 shows the profile of the gate charge Q_(g) 502 as a function ofthe gate-substrate voltage V_(GB) 503 that is present, and the gatecharge profile 501, which can be divided into three regions 504, 505,506.

A first region 504 is referred to as the accumulation region, a secondregion 505 represents the depletion region of the ferroelectrictransistor and a third region 506 represents the inversion region of thesaid transistor.

In order to programme a ferroelectric transistor which forms a memorycell, the ferroelectric transistor is brought into its inversion region506.

In order that a ferroelectric transistor which is adjacent to theferroelectric transistor is not likewise programmed in an undesirablemanner, it must be ensured according to the invention that the formertransistor is not brought into its respective inversion region 506.

As is explained in more detail below, this is ensured by the suitablechoice of a gate-source voltage V_(GS), the gate-source voltage V_(GS)being applied to the non-selected cells, that is to say the furtherferroelectric transistors 106, 107, 108, in such a way that it is lessthan the threshold voltage V_(th), which is dependent on the respectivepolarization of the ferroelectric transistor, in other words thefollowing holds true:V _(GS) −V _(th) +F(P _(FE))≦0,  (1)where F(P_(FE)) designates a function of the ferroelectric polarizationP_(FE) of the further ferroelectric transistor.

In FIG. 4, the step of programming the first ferroelectric transistor105 is represented symbolically in a further block 402.

Essentially at the same time, an electric voltage of the same value ofthe storage voltage 141 is in each case applied to the third bit line113 and the fourth bit line 114, as is illustrated in FIG. 6 b in thediagram 610, in which a voltage profile 611 of the electric voltage 612in each case applied to the third bit line 113 and the fourth bit line114 is illustrated as a function of the time 613 in seconds.

In order to illustrate this driving, FIG. 6 a again illustrates, in afurther diagram 600, the electric voltage 601, applied to the first wordline 109, as a function of the time 602 in a voltage profile 603.

It should be noted that, in accordance with this exemplary embodiment,the electric voltage applied to the first word line 109 in theprogramming region 604 has the same value as the electric voltage whichis in each case applied to the third bit line 113 and to the fourth bitline 114.

FIG. 6 c shows, in a further polarization diagram 620, the profile ofthe polarization 621 of the second ferroelectric transistor 106 duringthe programming of the first ferroelectric transistor 105, as isillustrated in FIG. 1 b to FIG. 1 d, as a function of the gate-substratevoltage V_(GB) 622.

As can be gathered from the further polarization diagram 620, thewidening of the second plateau region 623 is achieved by the suitableapplication of the gate-source voltage, specifically by the choice ofthe respective drain voltage and source voltage to be applied to thefurther ferroelectric transistors 106, 107, 108 in a manner dependent onthe respective programming voltage and thus dependent on the respectiveelectric voltage present at the gate.

An alteration of the state of the further ferroelectric transistors 106,107, 108 is avoided as a result of the widening of the second plateauregion 623.

As can be gathered from FIG. 6 c, the second ferroelectric transistor106 does not undergo a transition from its initial state 624 “0” to afinal state “1” 625, since it cannot surmount the plateau region 623along the hysteresis loop 626, as is symbolized by the arrows 627 inFIG. 6 c.

In this connection, it should be noted that, in accordance with thisexemplary embodiment, both the gate potential and the substratepotential are fixedly predetermined.

The two voltages that can be chosen at the source and drain contacts ofthe further ferroelectric transistors 106, 107 are driven in such a waythat it holds true that the source voltage V_(S) is equal to the applieddrain voltage V_(D) and the respective applied gate voltage V_(G), sothat the following holds true:V _(GS) =V _(GD)=0,  (2)and thusV _(GS) =V _(GD) ≦V _(th) −F(P _(FE)).  (3)

On account of the matrix arrangement from FIG. 1, there are present atthe ferroelectric transistor 108 the gate voltage V_(G)=0, a sourcevoltage and a drain voltage of, for example, V_(S)=V_(D)=5 V and also abulk voltage (substrate voltage) V_(B)=0 V. These voltages, too, do notalter the state of the ferroelectric polarization.

If the following holds true for the ferroelectric transistor 108:V _(GB) ≦V _(th) −V _(BS) −F(P _(FE)),  (4)then the ferroelectric transistor 108 is also in inversion or possiblyin accumulation.It should be ensured that

-   1. the n-channel ferroelectric transistor does not enter into    inversion, and-   2. as a result of the bulk-source voltage V_(BS), the ferroelectric    transistor does not enter into accumulation more deeply than for the    case where V_(BS)=0 holds true.

This ensures that the respective further ferroelectric transistor 106,107, 108 which is driven in the manner described above is operated inits depletion region 505 and not in its inversion region 506, therebyavoiding undesirable reprogramming of the respective furtherferroelectric transistor 106, 107.

This can be ensured very simply in particular when the respectiveferroelectric transistor has a gradient of the gate charge curve 501that is chosen to be sufficiently small in the depletion region 505 ofthe said transistor.

Generally, a ferroelectric transistor and thus the further electrictransistors 106, 107, 108 are operated in their depletion region 505during the read-out of the first ferroelectric transistor 105 if thefollowing holds true for the gate-source voltage V_(GS) of therespective further ferroelectric transistor 106, 107, 108:V _(FB) −F(P _(FE))≦V _(GS) ≦V _(th) −F(P _(FE)),  (5)where

-   -   V_(FB) designates the flat-band voltage of the further        ferroelectric transistor,    -   V_(GS) designates the gate-source voltage of the further        ferroelectric transistor,    -   V_(th) designates the threshold voltage of the further        ferroelectric transistor,    -   F(P_(FE)) designates a function of the ferroelectric        polarization P_(FE) of the further ferroelectric transistor.

In accordance with this exemplary embodiment, the threshold voltageV_(th) is prescribed in accordance with the following specification:V _(th) =V _(FB)+2Φ_(F)+γ√{square root over (2Φ_(F) +U _(SB))},  (6)where $\begin{matrix}{{\gamma = {\frac{1}{C_{Stack}^{\prime}}\sqrt{q^{N}A^{\quad{2\quad ɛ}}0^{\quad ɛ}S\quad i}}},} & (7)\end{matrix}$where γ designates the substrate control factor and $\begin{matrix}{{\Phi_{F} = {\frac{k\quad T}{q}\ln\frac{N_{A}}{n_{i}}}},} & (8)\end{matrix}$where Φ_(F) designates the Fermi potential and C′_(Stack) designates thegate stack capacitance of the respective further ferroelectrictransistor 106, 107, 108.

In accordance with the exemplary embodiment, the parameter values listedin the following table were used for the parameters present in the abovespecifications:

Parameter Value Unit P_(s) 0.1 μC/cm² P_(r) 0.08 μC/cm² Ec 30 kV/cmt_(fe) 180 nm t_(ox) 20 nm ε_(f) 250 ε_(OX) 11.7 A 2*10⁴  μm² N_(A)2*10¹⁵ cm⁻³ V_(FB) 0 V V_(D) 0.3 V V_(S) 0 V V_(B) 0 V

A number of alternatives to the exemplary embodiment presented above areexplained in more detail below.

The invention is not restricted to the above-described concrete form ofa memory matrix, in particular is not restricted to a memory matrixhaving four memory cells. The invention can be used in the context of anarbitrarily configured memory matrix having an arbitrary number ofmemory cells, that is to say of ferroelectric transistors as memorycells.

It should be noted in this connection that the above-describedprogramming scheme according to the invention can also be applied to oneor more selected memory cells whose state is not intended to be altered.

By way of example, all the memory cells may be initialized with thelogic value “0” at the beginning of the programming scheme. If a logicvalue “0” is to be stored, i.e. written, in a selected memory cell(V_(G)=high for this memory cell), then its state is not altered.

In order to ensure this, the following voltages are applied to therespective memory cell whose state is not intended to be altered:V _(G) =V _(S) =V _(D)=High.  (9)

Consequently, the state of the selected memory cell is not reprogrammedin this case.

Furthermore, a memory cell can also have a plurality of transistors, inparticular a plurality of ferroelectric transistors.

The following publications are cited in this document:

-   [1] T. Nakamura et al. A Single-Transistor Ferroelectric Memory    Cell, IEEE International Solid-State Circuits Conference, ISSCC95,    Session 4, Technology Directions: Displays, Photonics and    Ferroelectric Memories, pp. 68-69, 1995-   [2] Jong-Son Lyu et al., Metal-Ferroelectric-Semiconductor    Field-Effect Transistor (MFSFET) for Single Transistor Memory by    Using Poly-Si Source/Drain and BaMgF₄ Dielectric, IEDM 1996, pp.    503-506, 1996-   [3] U.S. Pat. No. 6,067,244    List of Reference Symbols-   100 Memory matrix-   101 Memory cell-   102 Memory cell-   103 Memory cell-   104 Memory cell-   105 First ferroelectric transistor-   106 Second ferroelectric transistor-   107 Third ferroelectric transistor-   108 Fourth ferroelectric transistor-   109 First word line-   110 Second word line-   111 First bit line-   112 Second bit line-   113 Third bit line-   114 Fourth bit line-   115 Gate of first ferroelectric transistor-   116 Gate of second ferroelectric transistor-   117 Gate of third ferroelectric transistor-   118 Gate of fourth ferroelectric transistor-   119 Source of first ferroelectric transistor-   120 Source of third ferroelectric transistor-   121 Drain of first ferroelectric transistor-   122 Drain of third ferroelectric transistor-   123 Source of second ferroelectric transistor-   124 Source of fourth ferroelectric transistor-   125 Drain of second ferroelectric transistor-   126 Drain of fourth ferroelectric transistor-   127 Read-out/storage control device-   128 Bulk terminal of first ferroelectric transistor-   129 Bulk terminal of second ferroelectric transistor-   130 Bulk terminal of third ferroelectric transistor-   131 Bulk terminal of fourth ferroelectric transistor-   132 Electrical line-   133 Electrical line-   140 First voltage diagram-   141 Voltage profile-   142 Electric voltage-   143 Time-   144 Programming region-   150 Seond voltage diagram-   151 Voltage profile-   152 Electric voltage-   153 Time-   160 Polarization diagram-   161 Polarization-   162 Gate-substrate voltage-   163 Polarization profile-   164 Initial state-   165 Final state-   166 Hysteresis curve-   167 Arrows-   168 First plateau region-   169 Second plateau region-   200 Profile of ferroelectric polarization in the gate of a    ferroelectric transistor as a function of the gate voltage-   201 Ferroelectric polarization in the gate of a ferroelectric    transistor-   202 Gate voltage-   203 Hysteresis loop-   204 First distinguishable polarization state-   205 Second distinguishable polarization state-   206 First non-distinguishable polarization state-   207 Second non-distinguishable polarization state-   300 Ferroelectric transistor-   301 Substrate-   302 Source region-   303 Drain region-   304 Silicon oxide region-   305 Silicon oxide region-   306 Dielectric intermediate layer-   307 Channel region-   308 Ferroelectric layer-   309 Metallic gate electrode-   310 Contact-   311 Contact-   312 Contact-   313 Protective layer-   401 Application of storage voltage to the first word line-   402 Application of storage voltage to the first word line-   403 Application of drain voltages and source voltages to the further    ferroelectric transistors-   500 Charge diagram-   501 Gate charge curve-   502 Gate charge-   503 Gate-substrate voltage-   504 Accumulation region of ferroelectric transistor-   505 Depletion region of ferroelectric transistor-   506 Conversion region of ferroelectric transistor-   600 Diagram-   601 Electric voltage-   602 Time-   603 Voltage profile-   604 Programming region-   610 Diagram-   611 Voltage profile-   612 Electric voltage-   613 Time-   620 Polarization diagram-   621 Polarization-   622 Gate-substrate voltage-   623 Second plateau region-   624 Initial state-   625 Final state-   626 Hysteresis loop-   627 Arrow

1. Method for reading out a state from a ferroelectric transistor of amemory cell which is arranged in a memory matrix with a plurality offurther memory cells with further ferroelectric transistors, the methodcomprising: reading the state is out from the ferroelectric transistor;driving at least one further ferroelectric transistor in the memorymatrix during the read-out of the state in such a way that it isoperated in its depletion region; and operating the furtherferroelectric transistor in the depletion region by the furtherferroelectric transistor being driven in such a way that the followingholds true:V _(FB) −F(P _(FE))≦V _(GS) ≦V _(th) −F(P _(FE)), where V_(FB)designates the flat-band voltage of the further ferroelectrictransistor; V_(GS) designates the gate-source voltage of the furtherferroelectric transistor; V_(th) designates the threshold voltage of thefurther ferroelectric transistor; and F(P_(FE)) designates a function ofthe ferroelectric polarization P_(FE) of the further ferroelectrictransistor.
 2. Method according to claim 1, further comprising readingout the state from the ferroelectric transistor by a read-out voltagebeing applied to the gate electrode of the ferroelectric transistor, forthe purpose of reading out the state.
 3. Method according to claim 1 or2, further comprising operating the further ferroelectric transistor inthe depletion region by the further ferroelectric transistor beingdriven in such a way that the gate-source voltage present at the furtherferroelectric transistor is less than the threshold voltage of the saidtransistor minus a term which is dependent on the ferroelectricpolarization.
 4. Method according to claim 1, further comprisingoperating the further ferroelectric transistor in the depletion regionby the further ferroelectric transistor being driven in such a way thatthe gate voltage applied to the further ferroelectric transistor isequal to the source voltage applied to the further ferroelectrictransistor and the drain voltage applied to the further ferroelectrictransistor.
 5. Method according to claim 1, further comprising using aplurality of transistors in at least one memory cell of the memorymatrix.
 6. A Memory matrix comprising: a plurality of memory cellsconnected to one another, at least some of the memory cells having atleast one ferroelectric transistor; a read-out control device, whichcontrols a read-out of a state from ferroelectric transistor of a memorycell of the memory matrix; the read-out control device being set up insuch a way that the state is read out from the ferroelectric transistor;at least one further ferroelectric transistor in the memory matrix, theat least one further ferroelectric transistor being driven during theread-out the state in such a way that it is operated in its depletionregion; and setting up the read-out control device in such a way thatthe further ferroelectric transistor is driven so that the followingholds true:V _(FB) −F(P _(FE))≦V _(GS) ≦V _(th) −F(P _(FE)), where V_(FB)designates the flat-band voltage of the further ferroelectrictransistor; V_(GS) designates the gate-source voltage of the furtherferroelectric transistor; V_(th) designates the threshold voltage of thefurther ferroelectric transistor; and F(P_(FE)) designates a function ofthe ferroelectric polarization P_(FE) of the further ferroelectrictransistor.
 7. Memory matrix according to claim 6, further comprisingsetting up the read-out control device in such a way that a read-outvoltage is applied to the gate electrode of the ferroelectrictransistor, for the purpose of reading out the state.
 8. Memory matrixaccording to claim 6, further comprising setting up the read-out controldevice in such a way that the further ferroelectric transistor is drivenin such a way that the gate-source voltage present at the furtherferroelectric transistor is less than the threshold voltage of the saidtransistor minus a term which is dependent on the ferroelectricpolarization.
 9. Memory matrix according to one of claims 6 to 8, inwhich at least one memory cell of the memory matrix has a plurality oftransistors.
 10. Memory matrix according to claim 6, in which theread-out control device is set up in such a way that the furtherferroelectric transistor is driven so that the gate voltage applied tothe further ferroelectric transistor is equal to the source voltageapplied to the further ferroelectric transistor and the drain voltageapplied to the further ferroelectric transistor.
 11. Method for storinga state in a ferroelectric transistor of a memory cell which is arrangedin a memory matrix with a plurality of further memory cells with furtherferroelectric transistors, the method comprising: storing the state inthe ferroelectric transistor; driving the at least one furtherferroelectric transistor in the memory matrix during the storage of thestate in such a way that it is operated in its depletion region; andoperating the further ferroelectric transistor in the depletion regionby the further ferroelectric transistor being driven in such a way thatthe following holds true:V _(FB) −F(P _(FE))≦V _(GS) ≦V _(th) −F(P _(FE)), where V_(FB)designates the flat-band voltage of the further ferroelectrictransistor; V_(GS) designates the gate-source voltage of the furtherferroelectric transistor; V_(th) designates the threshold voltage of thefurther ferroelectric transistor; and F(P_(FE)) designates a function ofthe ferroelectric polarization P_(FE) of the further ferroelectrictransistor.
 12. Method according to claim 11, further comprising storingthe state in the ferroelectric transistor by a storage voltage beingapplied to the gate electrode of the ferroelectric transistor forreading out the state.
 13. Method according to claim 11 or 12, furthercomprising operating the further ferroelectric transistor in thedepletion region by the further ferroelectric transistor being driven insuch a way that the gate-source voltage present at the furtherferroelectric transistor is less than the threshold voltage of the saidferroelectric transistor minus a term which is dependent on theferroelectric polarization.
 14. Method according to claim 11, furthercomprising operating the further ferroelectric transistor in thedepletion region by the further ferroelectric transistor being driven insuch a way that the gate voltage applied to the further ferroelectrictransistor is equal to the source voltage applied to the furtherferroelectric transistor and the drain voltage applied to the furtherferroelectric transistor.
 15. Method according to claim 11, furthercomprising using a plurality of transistors in at least one memory cellof the memory matrix.
 16. A memory matrix comprising: a plurality ofmemory cells connected to one another, at least some of the memory cellshaving at least one ferroelectric transistor; a storage control device,which controls the storage of a state in a ferroelectric transistor of amemory cell of the memory matrix; the storage control device being setup in such a way that the state is stored in the ferroelectrictransistor; at least one further ferroelectric transistor in the memorymatrix, the at least one further ferroelectric transistor being drivenduring the storage of the state in such a way that it is operated in itsdepletion region, wherein the storage control device is set up in such away that the further ferroelectric transistor is driven so that thefollowing holds true:V _(FB) −F(P _(FE))≦V _(GS) ≦V _(th) −F(P _(FE)), where V_(FB)designates the flat-band voltage of the further ferroelectrictransistor; V_(GS) designates the gate-source voltage of the furtherferroelectric transistor; V_(th) designates the threshold voltage of thefurther ferroelectric transistor; and F(P_(FE)) designates a function ofthe ferroelectric polarization P_(FE) of the further ferroelectrictransistor.
 17. Memory matrix according to claim 16, further comprisingsetting up the storage control device in such a way that a storagevoltage is applied to the gate electrode of the ferroelectrictransistor, for the purpose of storing the state.
 18. Memory matrixaccording to claim 16, further comprising setting up the storage controldevice in such a way that the further ferroelectric transistor is drivenin such a way that the gate-source voltage present at the furtherferroelectric transistor is less than the threshold voltage of the saidtransistor minus a term which is dependent on the ferroelectricpolarization.
 19. Memory matrix according to claim 16 to 18, in which atleast one memory cell of the memory matrix has a plurality oftransistors.
 20. Memory matrix according to claim 16, further comprisingsetting up the storage control device in such a way that the furtherferroelectric transistor is driven so that the gate voltage applied tothe further ferroelectric transistor is equal to the source voltageapplied to the further ferroelectric transistor and the drain voltageapplied to the further ferroelectric transistor.